- 您现在的位置：买卖IC网 > Sheet目录450 > ISL5216EVAL1 (Intersil)EVALUATION BOARD FOR ISL5216KI
ISL5216
65.536MHz/4 = 16.384MHz, where the factor of 4 is the CIC
decimation we have chosen.
Each channel computes the same sequence, offset by one
output sample from the previous sample (see IWA = *00Bh).
Each channel decimates down to 2.048M and then the
channels are multiplexed together in the output formatter to
get the desired 8.192MSPS. The input sample rate to the
final filter of each channel must meet Nyquist requirements
for the final output to assure that no information is lost due to
aliasing.
SAMPLE FILTER #4 PROGRAM
The filter sequencer is programmed via an instruction RAM
and several control registers. These are described below.
Instruction RAMs
The filter compute engine is controlled by a simple
sequencer supporting up to 32 steps. Each step can be a
filter or one of four sequence flow instructions—wait, jump
(conditional or unconditional), load loop counter, or NOP.
There are 128 bits per instruction word with each word
consisting of condition code selects, FIR parameters and
data routing controls. Not all of the instruction word bits are
used for all instruction types. The actual sequencer
STEP
0
1
2
INSTRUCTION
Wait for enough input samples (8 in this case)
FIR
type = even symmetry
44 taps
decimate by 8
compute one output
memory block size 64
memory block start at 0
coefficient block start at 64
step size 1
output to AGC
offset memory read pointers by 0, -2, -4, -6
Jump, Unconditional, to 0
instruction is only 9 bits. The rest of the bits are used for filter
parameters or for the loop counter preload. Each sequence
step is loaded by the microprocessor in four 32-bit writes.
The mapping of the bit fields for the instruction types is
shown in the instruction bit field table that follows. These FIR
instruction words can be generated using software tools
provided with the ISL5216 evaluation board.
When the filter is reset, the instruction pointer is set to 31
(the last instruction step). The read and write pointers are
initialized on reset, so a reset must be done when the
channel is initialized or restarted.
A fixed offset can be added to the starting read address of
one of the filters in the program. This function is provided to
offset the data reads of the filters in a polyphase filter bank;
all filters in the bank will write the same data to the same
The number of FIR taps available for these requirements is
calculated as follows:
65536/2048 = 32 clocks
minus (8 writes + 1 wait + 1 jump = 10 clocks)
= 22 clocks
Therefore, the number of taps available is:
22 x 2 = 44 taps.
Multiplexing the four outputs gives a final output sample rate
of 8.192MSPS.
The impulse response is 44 taps at 16.384M or 22 output
samples (11 symbols at 4.096M).
The AGC loop filter output of channel 4 can be routed to
control the forward AGC gain control of all four channels.
This assures that the gains of the four back end sections are
the same. The gain error, however, is only computed from
every fourth output sample.
The back end processing sections of two or more ISL5216s
can be combined using the same polyphase approach, but
the AGC gain from one part cannot be shared with another
part (except via the μ P interface), so polyphase filter using
multiple parts would typically usually use a fixed gain.
17
RAM location. To offset the computations the RAM read
address is offset. See IWA = *00Bh for details.
The instruction word bits (127:0) are assigned to memory
words as follows:
31:0 to destination C C C C 0 0 0 1 0 x x x x x 0 0
63:32 to destination C C C C 0 0 0 1 0 x x x x x 0 1
95:64 to destination C C C C 0 0 0 1 0 x x x x x 1 0
127:96 to destination C C C C 0 0 0 1 0 x x x x x 1 1
where CCCC is the channel number and xxxxx is the
instruction sequence step number (0–31 decimal). Note the
μ PHold bit in the filter compute engine control register
(IWA = *00Ah) must be set for the microprocessor to read
from or write to the instruction or coefficient RAMs.
FN6013.3
July 13, 2007
发布紧急采购，3分钟左右您将得到回复。
相关PDF资料
ISL5217EVAL1
EVALUATION BOARD FOR ISL5217KI
ISL5239EVAL1
EVALUATION BOARD FOR ISL5239
ISL5239KIZ
IC LINEARIZER PRE-DISTORT 196BGA
ISL5416EVAL1
EVALUATION PLATFORM FOR ISL5416
ISL55005IEZ-T7
IC AMP MMIC BIPO BROADBND SC70-6
ISL55007IEZ-T7
IC AMP MMIC BIPO BROADBND SC70-6
ISL55008IEZ-T7
IC AMP MMIC BIPO BROADBND SC70-6
ISL55009IEZ-T7
IC AMP MMIC BIPO BROADBND SC70-6
相关代理商/技术参数
ISL5216KI
功能描述:上下转换器 QUAD DIGITAL DOWNCONVERTER,IND TEMP,0.8M RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128
ISL5216KI-1
功能描述:上下转换器 QUAD DIGITAL DOWNCONVERTER,IND TEMP,1.OMM PITCH BGA PACKAG RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128
ISL5216KI-1Z
功能描述:上下转换器 W/ANL QD DIG DWNCNVRTR 1 OM PITCH RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128
ISL5216KIZ
功能描述:上下转换器 W/ANNEAL QD DIGTL DWNCNVRTR IND TEMP RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128
ISL5217
制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Quad Programmable Up Converter
ISL5217_05
制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Quad Programmable Up Converter
ISL5217EVAL1
功能描述:EVALUATION BOARD FOR ISL5217KI RoHS:是 类别:RF/IF 和 RFID >> RF 评估和开发套件，板 系列:- 标准包装:1 系列:- 类型:GPS 接收器 频率:1575MHz 适用于相关产品:- 已供物品:模块 其它名称:SER3796
ISL5217KI
功能描述:上下转换器 196BGA,-40+85C PROGRAMMABLE QUAD UP CONVERTER RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128